Two facets of prior art semiconductor constructions are pertinent to exemplary aspects of the present invention. One is the utilization of bond pads and redistribution layers, and the other is the utilization of fuses. Both facets are described with reference to a prior art semiconductor construction 10 shown in FIGS. 1 and 2.
Construction 10 comprises a semiconductor substrate 12 having a surface 14 of insulative material. The substrate 12 also comprises a first series of bond pads 16 extending vertically along a central region of the top view of FIG. 1. The bond pads 16 are beneath surface 14 in the top view, and accordingly are shown in dashed-line view in FIG. 1. Semiconductor substrate 12 comprises a package having a semiconductor die (such as, for example, a silicon wafer die) (not shown) and integrated circuitry associated therewith (not shown) covered by insulative material 14. Bond pads 16 electrically interconnect with such integrated circuitry, and are utilized for providing electrical connection between the integrated circuitry contained within the package of construction 10 and other circuitry (not shown) external of construction 10. For instance, construction 10 can comprise a memory chip and bond pads 16 can be utilized for electrically connecting the memory chip with other circuitry, including, for example, circuitry leading to a computer processor.
Bond pads 16 are frequently too tightly packed to readily enable direct connection between bond pads 16 and other circuitry external of the pads. Accordingly, another set of pads 18 is formed, and redistribution layers 20 are provided to electrically connect pads 18 with pads 16. Pads 18 would typically not be covered by insulative material 14, so that the pads 18 are exposed for electrical connection to circuitry external of construction 10. In contrast, redistribution layers 20 typically are covered by insulative material 14 to protect such redistribution layers, and accordingly the redistribution layers are shown in dashed-line view in FIG. 1. Bond pads 18 are significantly more disperse from one another than are bond pads 16.
As discussed previously, the bond pads 16 and 18 are utilized for electrically connecting to circuitry associated with substrate 12, and accordingly for providing electrical access to such circuitry. Pads 16 and 18 are thus exemplary access nodes.
FIG. 2 shows a cross-sectional view along the line 2-2 of FIG. 1, and illustrates an exemplary assembly of bond pads 16 and 18, and redistribution layer 20. The assembly includes a base 22 which can comprise numerous layers of insulative and conductive material. In particular aspects, base 22 will comprise the semiconductor die and integrated circuitry referred to above. For purposes of interpreting this disclosure and the claims that follow, it is useful to define the terms “semiconductor substrate” and “substrate”. Accordingly, the terms “semiconductive substrate” and “semiconductor substrate” are to be understood in this document to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” is to be understood to refer to any supporting structure, including, but not limited to, the semiconductive substrates described above. Accordingly, base 22 can be considered a semiconductor substrate if the base comprises a semiconductor die. Also, base 22 in combination with one or more of the layers thereover can be considered a semiconductor substrate if the base comprises a semiconductor die.
An insulative material 24 is over base 22, and pads 16 are within openings extending through insulative material 24. Insulative material 24 can comprise any suitable material, including, for example, silicon dioxide, silicon nitride, borophosphosilicate glass (BPSG), etc. Additionally, pad 16 can comprise any suitable conductive material or combination of conductive materials, and in particular aspects will comprise, consist essentially of, or consist of one or more metals, metal alloys, or metal-containing compounds. For instance, pad 16 can comprise, consist essentially of, or consist of one or more of copper, silver, aluminum, gold and nickel. Although pad 16 is shown comprising a single homogeneous layer, it is to be understood that pad 16 can comprise multiple layers.
Redistribution layer 20 is formed over insulative material 24 and in electrical connection with pad 16. Redistribution layer 20 can comprise any suitable conductive material or combination of conductive materials, and in particular aspects will comprise, consist essentially of, or consist of one or more of metals, metal compounds, metal alloys, and/or conductively-doped semiconductor material (such as conductively-doped silicon).
An insulative material 26 is formed over redistribution layer 20 and over insulative material 24. Insulative material 26 can be any suitable material, including, for example, BPSG, phosphosilicate glass (PSG), polyimide, etc. Insulative material 26 comprises the upper surface 14 shown in FIG. 1.
Bond pads 18 are formed within openings in insulative material 14, and in electrical connection with redistribution layer 20. Bond pads 18 can comprise any suitable electrically conductive material or combination of materials. In particular aspects, bond pads 18 will comprise a nickel-containing layer adjacent redistribution layer 20, and a gold-containing layer over the nickel-containing layer.
As discussed previously with reference to FIG. 1, bond pads 18 are ultimately utilized for forming electrical connections to circuitry external of construction 10. Such connections will typically be achieved through utilization of solder balls, and specifically a ball grid array will be formed over the pads 18 of the FIG. 1 construction. An exemplary solder ball 28 is diagrammatically illustrated in FIG. 2 as being electrically connected with shown bond pad 18. Solder ball 28 is shown in dashed-line view in FIG. 2 to indicate that the solder ball structure is only shown in FIG. 2, and not in FIG. 1.
FIG. 1 shows a region 30 demarcated by a dashed-line square. Such region is a diagrammatic illustration of a fuse box region (or alternatively a fuse access region). The region 30 is shown as a square and referred to as a fuse “box,” but it is to be understood that fuse box region 30 can have any suitable peripheral shape, including, for example, curved shapes, polygonal shapes, etc. Fuses are provided to extend within region 30 of construction 10 so that various circuit elements within the construction can be electrically decoupled from other elements. Numerous uses of fuses are known to persons of ordinary skill in the art. For instance, the fuses can be utilized for disconnecting circuit elements which are utilized only for testing of circuitry components associated with construction 10, for disconnecting circuit elements which are found to be faulty through testing of the circuitry so that redundant circuitry can be utilized in place of the faulty circuitry, etc.
The fuse box location 30 will typically comprise a number of fuses beneath surface 14. The fuses can be configured to be broken (i.e. “blown”) with appropriate energy input, such as, for example, laser-energy input and/or thermal-energy input. It is desired that the material over the fuses be uniformly thick across the fuses so that the energy utilized to penetrate through the material and break the fuses is uniform across the fuses in the fuse box region. Numerous difficulties are encountered, however, in attempting to form a uniform-thickness material across all of the fuses contained within fuse box region 30. Accordingly, some aspects of the invention described herein pertain to methodologies which can enable a substantially uniform thickness of material to be provided over the fuses within a fuse box region. However, although the invention was motivated from this perspective, the invention is not so limited. Rather, the invention is only limited by the accompanying claims as literally worded, and in accordance with the doctrine of equivalents.